1.3.5
00001 00006 /* 00007 * The contents of this file are subject to the Mozilla Public License 00008 * Version 1.0 (the "License"); you may not use this file except in 00009 * compliance with the License. You may obtain a copy of the License 00010 * at http://www.mozilla.org/MPL/ 00011 * 00012 * Software distributed under the License is distributed on an "AS IS" 00013 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See 00014 * the License for the specific language governing rights and 00015 * limitations under the License. 00016 * 00017 * The Original Code is legOS code, released October 17, 1999. 00018 * 00019 * The Initial Developer of the Original Code is Markus L. Noga. 00020 * Portions created by Markus L. Noga are Copyright (C) 1999 00021 * Markus L. Noga. All Rights Reserved. 00022 * 00023 * Contributor(s): Markus L. Noga <markus@noga.de> 00024 */ 00025 00026 #ifndef __sys_h8_h__ 00027 #define __sys_h8_h__ 00028 00029 #ifdef __cplusplus 00030 extern "C" { 00031 #endif 00032 00033 // 16 bit timer registers 00034 // 00035 00037 extern unsigned char T_IER; 00038 00040 extern volatile unsigned char T_CSR; 00041 00043 extern volatile unsigned T_CNT; 00044 00046 extern unsigned T_OCRA; 00047 00049 /* address shared with T_OCRA */ 00050 extern unsigned T_OCRB; 00051 00053 extern unsigned char T_CR; 00054 00056 extern unsigned char T_OCR; 00057 00058 00060 extern volatile unsigned T_ICRA; 00061 00063 extern volatile unsigned T_ICRB; 00064 00066 extern volatile unsigned T_ICRC; 00067 00069 extern volatile unsigned T_ICRD; 00070 00071 // 00072 // TIER bitmasks 00073 // 00074 #define TIER_ENABLE_ICA 0x80 // input capture IRQ enables 00075 #define TIER_ENABLE_ICB 0x40 00076 #define TIER_ENABLE_ICC 0x20 00077 #define TIER_ENABLE_ICD 0x10 00078 #define TIER_ENABLE_OCA 0x08 // output compare IRQ enables 00079 #define TIER_ENABLE_OCB 0x04 00080 #define TIER_ENABLE_OF 0x02 // overflow IRQ enable 00081 #define TIER_RESERVED 0x01 // always set. 00082 00083 // 00084 // TCSR bitmasks 00085 // 00086 #define TCSR_ICA 0x80 // input capture events 00087 #define TCSR_ICB 0x40 00088 #define TCSR_ICC 0x20 00089 #define TCSR_ICD 0x10 00090 #define TCSR_OCA 0x08 // output compare events 00091 #define TCSR_OCB 0x04 00092 #define TCSR_OF 0x02 // overflow event 00093 #define TCSR_RESET_ON_A 0x01 // reset counter on match A 00094 00095 // 00096 // TCR bitmasks 00097 // 00098 #define TCR_A_RISING 0x80 // input capture on rising 00099 #define TCR_B_RISING 0x40 // edge. if not set -> lower 00100 #define TCR_C_RISING 0x20 00101 #define TCR_D_RISING 0x10 00102 #define TCR_BUFFER_A 0x08 // buffer A in C 00103 #define TCR_BUFFER_B 0x04 // buffer B in D 00104 #define TCR_CLOCK_2 0x00 // clock = pclock / 2 00105 #define TCR_CLOCK_8 0x01 // clock = pclock / 8 00106 #define TCR_CLOCK_32 0x02 // clock = pclock / 32 00107 #define TCR_CLOCK_EXT 0x03 // external clock, rising edge 00108 00109 // 00110 // TOCR bitmasks 00111 // 00112 #define TOCR_OCRA 0x00 // select register to write 00113 #define TOCR_OCRB 0x10 00114 #define TOCR_ENABLE_A 0x08 // enable output signals 00115 #define TOCR_ENABLE_B 0x04 00116 #define TOCR_HIGH_LEVEL_A 0x02 // set output to high for match 00117 #define TOCR_HIGH_LEVEL_B 0x01 00118 00119 00120 // 00121 // 8 bit timer registers 00122 // 00123 00125 extern unsigned char STCR; 00126 00128 extern unsigned char T0_CR; 00129 00131 extern volatile unsigned char T0_CSR; 00132 00134 extern unsigned char T0_CORA; 00135 00137 extern unsigned char T0_CORB; 00138 00140 extern volatile unsigned char T0_CNT; 00141 00142 00144 extern unsigned char T1_CR; 00145 00147 extern volatile unsigned char T1_CSR; 00148 00150 extern unsigned char T1_CORA; 00151 00153 extern unsigned char T1_CORB; 00154 00156 extern volatile unsigned char T1_CNT; 00157 00158 00159 // 00160 // CR flag bitmasks 00161 // 00162 #define CR_ENABLE_IRQA 0x40 00163 #define CR_ENABLE_IRQB 0x80 00164 #define CR_ENABLE_IRQO 0x20 00165 00166 #define CR_CLEAR_NEVER 0x00 00167 #define CR_CLEAR_ON_A 0x08 00168 #define CR_CLEAR_ON_B 0x10 00169 #define CR_CLEAR_ON_EXTERN 0x18 00170 00171 // I don't define speeds here because the STCR bits are involved, too. 00172 // Also, speeds differ for T0 and T1. 00173 00174 00175 // 00176 // CSR bitmasks 00177 // 00178 #define CSR_MATCH_A 0x40 00179 #define CSR_MATCH_B 0x80 00180 #define CSR_OVERFLOW 0x20 00181 00182 #define CSR_IGNORE_B 0x00 00183 #define CSR_0_ON_B 0x04 00184 #define CSR_1_ON_B 0x08 00185 #define CSR_TOGGLE_ON_B 0x0c 00186 00187 #define CSR_IGNORE_A 0x00 00188 #define CSR_0_ON_A 0x01 00189 #define CSR_1_ON_A 0x02 00190 #define CSR_TOGGLE_ON_A 0x03 00191 00192 // 00193 // Serial port 00194 // 00195 00197 extern volatile unsigned char S_RDR; 00198 00200 extern unsigned char S_TDR; 00201 00203 extern unsigned char S_MR; 00204 00206 extern unsigned char S_CR; 00207 00209 extern volatile unsigned char S_SR; 00210 00212 extern unsigned char S_BRR; 00213 00215 extern unsigned char S_TCR; 00216 00217 // 00218 // register bitmasks 00219 // 00220 #define SMR_SYNC 0x80 // in sync mode, the other settings 00221 #define SMR_ASYNC 0x00 // have no effect. 00222 #define SMR_7BIT 0x40 00223 #define SMR_8BIT 0x00 00224 #define SMR_P_NONE 0x00 00225 #define SMR_P_EVEN 0x20 00226 #define SMR_P_ODD 0x30 00227 #define SMR_1STOP 0x00 00228 #define SMR_2STOP 0x08 00229 #define SMR_MP 0x04 // multiprocessing -> no parity 00230 // for mp, mpe in STRC must be set 00231 #define SMR_CLOCK 0x00 // clock rate for baud rate generator 00232 #define SMR_CLOCK_4 0x01 // pclock / 4 00233 #define SMR_CLOCK_16 0x02 // pclock / 16 00234 #define SMR_CLOCK_64 0x03 // pclock / 64 00235 00236 00237 #define SCR_TX_IRQ 0x80 // TIE transmit irq enable 00238 #define SCR_RX_IRQ 0x40 // RIE receive / recv err irq enable 00239 #define SCR_TRANSMIT 0x20 // enable transmission 00240 #define SCR_RECEIVE 0x10 // enable receiving 00241 #define SCR_MP_IRQ 0x08 // multiprocessing receive irq 00242 #define SCR_TE_IRQ 0x04 // TEI transmit end irq enable 00243 #define SCR_INT_CLOCK 0x00 // internal clock source 00244 #define SCR_EXT_CLOCK 0x02 // external clock source 00245 #define SCR_CLOCK_OUT 0x01 // output internal clock to SCK pin 00246 00247 00248 #define SSR_TRANS_EMPTY 0x80 // transmit buffer empty 00249 #define SSR_RECV_FULL 0x40 // receive buffer full 00250 #define SSR_OVERRUN_ERR 0x20 // overrun error 00251 #define SSR_FRAMING_ERR 0x10 // framing error 00252 #define SSR_PARITY_ERR 0x08 // parity error 00253 #define SSR_ERRORS 0x38 // all errors 00254 #define SSR_TRANS_END 0x04 // transmission end because buffer empty 00255 #define SSR_MP 0x02 // multiprocessor 00256 #define SSR_MP_TRANSFER 0x01 // multiprocessor bit transfer 00257 00258 00259 // 00260 // values for the bit rate register BRR 00261 // assuming CMR_CLOCK selected on 16 MHz processor 00262 // error <= 0.16% 00263 // 00264 00265 #define B2400 207 00266 #define B4800 103 00267 #define B9600 51 00268 #define B19200 25 00269 #define B38400 12 00270 00271 00272 // A/D converter 00273 // 00274 00276 extern volatile unsigned char AD_A_H; 00277 00279 00280 extern volatile unsigned char AD_A_L; 00281 00283 extern volatile unsigned char AD_B_H; 00284 00286 00287 extern volatile unsigned char AD_B_L; 00288 00290 extern volatile unsigned char AD_C_H; 00291 00293 00294 extern volatile unsigned char AD_C_L; 00295 00297 extern volatile unsigned char AD_D_H; 00298 00300 00301 extern volatile unsigned char AD_D_L; 00302 00303 00305 00306 extern volatile unsigned AD_A; 00307 00309 00310 extern volatile unsigned AD_B; 00311 00313 00314 extern volatile unsigned AD_C; 00315 00317 00318 extern volatile unsigned AD_D; 00319 00320 00322 extern volatile unsigned char AD_CSR; 00323 00325 extern unsigned char AD_CR; 00326 00327 00328 // 00329 // A/D CSR bitmasks 00330 // 00331 00332 #define ADCSR_END 0x80 00333 #define ADCSR_ENABLE_IRQ 0x40 00334 #define ADCSR_START 0x20 00335 #define ADCSR_SCAN 0x10 // enable scan mode 00336 #define ADCSR_TIME_266 0x00 // select A/D conversion time 00337 #define ADCSR_TIME_134 0x08 00338 00339 #define ADCSR_GROUP_0 0x00 // select scan group 00340 #define ADCSR_GROUP_1 0x04 00341 00342 #define ADCSR_AN_0 0x00 // first group of inputs to convert 00343 #define ADCSR_AN_1 0x01 00344 #define ADCSR_AN_2 0x02 00345 #define ADCSR_AN_3 0x03 // in scan mode: AN0-AN3 00346 00347 // 00348 // A/D CR bitmasks 00349 // 00350 00351 #define ADCR_EXTERN 0x80 // allow external triggering 00352 00353 00354 // 00355 // system control register 00356 // FIXME: incomplete 00357 00359 extern unsigned char SYSCR; 00360 00361 #define SYSCR_SOFTWARE_STANDBY 0x80 // software standby flag 00362 00363 // 00364 // I/O ports 00365 // 00366 00368 extern unsigned char PORT1_PCR; 00369 00371 extern unsigned char PORT2_PCR; 00372 00374 extern unsigned char PORT3_PCR; 00375 00376 00377 00379 extern unsigned char PORT1_DDR; 00380 00382 extern volatile unsigned char PORT1; 00383 00384 00386 extern unsigned char PORT2_DDR; 00387 00389 extern volatile unsigned char PORT2; 00390 00391 00393 extern unsigned char PORT3_DDR; 00394 00396 extern volatile unsigned char PORT3; 00397 00398 00400 extern unsigned char PORT4_DDR; 00401 00403 extern volatile unsigned char PORT4; 00404 00405 00407 extern unsigned char PORT5_DDR; 00408 00410 extern volatile unsigned char PORT5; 00411 00412 00414 extern unsigned char PORT6_DDR; 00415 00417 extern volatile unsigned char PORT6; 00418 00419 00421 extern volatile unsigned char PORT7; 00422 00423 00424 00426 extern volatile unsigned int WDT_CSR; 00427 00428 #define WDT_CSR_PASSWORD (0xA500) 00429 #define WDT_CSR_ENABLE (0x0020) 00430 #define WDT_CSR_MODE_WATCHDOG (0x0040) 00431 #define WDT_CSR_MODE_OVERFLOW (0x0000) 00432 #define WDT_CSR_WATCHDOG_NMI (0x0000) 00433 #define WDT_CSR_WATCHDOG_RES (0x0008) 00434 #define WDT_CSR_CLOCK_2 (0x0000) 00435 #define WDT_CSR_CLOCK_32 (0x0001) 00436 #define WDT_CSR_CLOCK_64 (0x0002) 00437 #define WDT_CSR_CLOCK_128 (0x0003) 00438 #define WDT_CSR_CLOCK_256 (0x0004) 00439 #define WDT_CSR_CLOCK_512 (0x0005) 00440 #define WDT_CSR_CLOCK_2048 (0x0006) 00441 #define WDT_CSR_CLOCK_4096 (0x0007) 00442 00444 extern volatile unsigned char WDT_CNT; 00445 00446 #define WDT_CNT_PASSWORD (0x5A00) 00447 #define WDT_CNT_CLEAR (0x0000) 00448 #define WDT_CNT_MSEC_64 (0x0006) 00449 00450 #ifdef __cplusplus 00451 } 00452 #endif 00453 00454 #endif // __sys_h8_h__
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brickOS is released under the
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Original code copyright 1998-2002 by the authors. |
1.3.5